`timescale 1ns/100ps

module i2c_master_tb;

parameter SYSCLK_PERIOD = 10;

reg SYSCLK;
reg i2c_slave_clk;
reg nRESET;
wire scl;
wire sda;

reg [7:0] slave_addr;
reg [7:0] reg_addr;
reg [7:0] reg_value;

pullup(scl);
pullup(sda);


initial
begin
	SYSCLK = 0;
	i2c_slave_clk = 0;
	nRESET = 0;
	slave_addr = 8'hA0;
	reg_addr = 8'h11;
	reg_value = 8'h55;
end


/*iverilog */
initial
begin            
    $dumpfile("i2c_master.vcd");        //生成的vcd文件名称
    $dumpvars(0, i2c_master_tb);    //tb模块名称
end
/*iverilog */

initial

begin
	#(SYSCLK_PERIOD * 2 )
        nRESET = 1'b1;
	#1300
		slave_addr <= 8'hA1;
		nRESET = 1'b0;
	#(SYSCLK_PERIOD * 2 )
        nRESET = 1'b1;
	#2000
		$finish;
end

always @(SYSCLK)
begin
	#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
end

always @(i2c_slave_clk)
begin
	#(SYSCLK_PERIOD / 4.0) i2c_slave_clk <= !i2c_slave_clk;
end


i2c_master i2c_master_0(
	.clk(SYSCLK),
	.rst_n(nRESET),
	.slave_addr(slave_addr),
	.reg_addr(reg_addr),
	.reg_value(reg_value),
	
	.scl(scl),
	.sda(sda)
);

i2c_slave i2c_slave_0(
	.clk(i2c_slave_clk),
	.rst_n(nRESET),
	
	.scl(scl),
	.sda(sda)
);

endmodule